1. Field of the Invention
The present invention relates to integrated circuits, and in particular, to predicting the soft error rate at logic nodes in integrated circuits.
2. Discussion of Related Art
Logic nodes in integrated circuits (“ICs”) have become increasingly susceptible to errors caused by radiation. Part of the reason for this increase lies with the efforts by IC manufacturers to reduce device sizes and decrease power usage. For example, to increase processing speeds, manufacturers have lowered both the capacitance of and the voltage across the logic nodes in the IC. At the same time, IC manufacturers have decreased the size of the logic nodes to decrease the overall size of the IC. By taking these actions, however, IC manufacturers have also decreased the charge used by the logic node, making them more vulnerable to interference by outside radiation. As a result, IC manufacturers have seen an increasing soft error rate, presumably caused by radiation incident at the logic nodes. A soft error occurs when only the data on a system is corrupted. The system components usually sustain no damage during the event. Because logic nodes manipulate, but do not store, data, the error rate at logic nodes is measured in terms of the soft error rate (“SER”), which is the number of failures per logic node over a period of time.
A soft error is typically the result of a sequence of events. A soft error begins with a single event upset (“SEU”) in which external radiation strikes an IC creating a pulse on a logic line. This radiation can come from a variety of sources. For example, as shown in FIG. 1, alpha particles can be emitted radioactivity from a variety of sources, such as from the contact material, the surrounding packaging, or even the semiconductor material itself. When these alpha particles strike the IC, they may create electron-hole pairs in the logic node, causing a pulse to form. In another example, the radiation may come from high energy neutrons coming from space, as shown in FIG. 2. The largest source of neutrons is extra-terrestrial. Therefore, until now, high energy neutrons have only created problems for ICs in space or at high altitude. With the decreasing amount of charge used by the logic node, however, these high energy neutrons are beginning to cause problems at sea-level as well. Furthermore, a single high energy neutron can cause a small reaction in which more than just one electron-hole pair is created. Accordingly, a high energy neutron does not need to directly impact a logic node to cause an SEU, and a single neutron can cause SEUs to occur in more than one logic node.
If a pulse caused by outside radiation is strong enough and of sufficient duration, the pulse may propagate through the IC as an erroneous signal. For today's technology, the pulse need only last less than about one pico-second for it to propagate through the IC. In addition, the charge needed to cause an SEU in present day devices is less than about 10 femto-coulombs. Further, the level of charge needed to cause an SEU will decrease as new technologies require less charge to operate. Moreover, the pulse duration needed to cause an SEU will continue to decrease as processor speeds increase. Accordingly, SER also promises to increase as processing speed increases and IC size decreases.
The pulse that results from an SEU propagates through the IC if it is produced at a time that matches the timing of the IC. Additionally, before the pulse can propagate, the logic path that it impacts must be enabled. For example, if the pulse goes through one input of an XOR gate, then the other input must be at a low state. Also, the pulse should be latched if it is to contribute to an SER. For example, a pulse that overlaps with a rising clock edge at the input to a latch will be latched, provided that the pulse is of sufficient duration to satisfy the set-up and hold times of the latch. If the pulse is latched, it may propagate through the IC, destroying data and causing a soft error in the IC. As the setup and hold times of latches decrease to accommodate increasing processor speeds, the probability that a pulse will satisfy the setup and hold times of a latch will correspondingly increase. Thus, the probability that an SEU will result in a soft error will continue to increase as IC technology advances.
Until recently, IC manufacturers have focused their efforts at improving the reliability of memory nodes for a variety of reasons. For one, memory nodes outnumber logic nodes on almost all ICs. Additionally, until recently, the charge used by logic nodes has usually been sufficient such that SER was relatively low for those nodes. Finally, no cost effective way existed to determine the SER on an IC. In fact, to determine the SER at a particular logic node, the IC manufacturer had to send an actual IC to a facility in Los Alamos, N.M., operated by integrated Robustness on Chips, or iRoC, for testing. iRoC would test the IC by bombarding it with different types of radiation to estimate the SER. Only after obtaining the results of the test of a physical IC could the IC manufacturer determine which logic nodes to improve. Then a new IC had to be fabricated and tested to determine if the changes actually improved the SER. This process has proven to be time-consuming and costly for IC manufacturers.
Therefore, there is a need to provide an improved method and system for estimating the SER of the logic nodes in an IC.